1. Field of the Invention
This invention relates to a semiconductor device and a process for fabricating the same, and more particularly to a bipolar semiconductor device having a dielectric isolation region of a U-groove structure filled with polycrystalline silicon (referred to as "polysilicon" hereinafter), and a process for fabricating the same.
2. Description of the Prior Art
In silicon LSIs (large scale integrated) circuits, a dielectric isolation region is commonly used to isolate electronic elements. There are a number of methods of isolating semiconductor device areas, such as p-n junction isolation, LOCOS method isolation, and U-groove structure isolation which is called as "trench isolation". Recently the LOCOS method isolation and the U-groove structure isolation are the main current. It has been known that U-groove structure requires narrow region for dielectric isolation as compared with LOCOS structure.
Dielectric isolation region of U-groove structure (referred to as "U-groove dielectric isolation region" hereinafter) was reported firstly in IDEM Tech. Digest, pp. 58-60, 1982. Before this report was already known the dielectric isolation region of V-groove structure formed on the major plane (100) of silicon crystal by mesa-etching. In this structure, dielectric breakdown voltage lowers with smaller V-groove width. In order to overcome the disadvantage of dielectric breakdown voltage like this, the aforementioned IDEM report proposed a U-groove dielectric isolation region.
The formation of a dielectric isolation region of a U-groove structure is carried out generally prior to the formation of semiconductor elements. Therefore, the semiconductor elements are seriously affected by the difference in thermal expansion coefficient between material with which the U-groove is filled and silicon substrate. The U-groove structures are divided into two types: in one type the U-groove is covered over the inner surface thereof with insulating films and filled with polysilicon which is extensively used for dielectric isolation in bipolar transistors. In the other type the U-groove is filled with a dielectric such as BPSG which is used mainly for dielectric isolation in MOS transistors.
In the first type structure, the surface of the polysilicon inside the U-groove is covered with an insulating film. The following specification will describe two recent examples: one is described in a Japanese Patent Laid-Open Application No. Sho. 61-22646; opened on Jan. 31, 1986. This application is presented to solve degradation of the properties of the semiconductor elements due to the stress at the upper edge of the U-groove. In this laid-open specification, a silicon oxide film deposited by a CVD process is used as the insulating film covering the surface of the polysilicon inside the U-groove (referred to as "U-groove polysilicon" hereinafter). Besides, two insulating films are formed covering the inner surface of the U-groove: a silicon oxide film being formed by thermal oxidation (referred to as "thermal-oxidation silicon oxide film" hereinafter) as the first layer, and a silicon oxide film being formed by the CVD process (referred to as "CVD silicon oxide film" hereinafter) as the second film. As the second layer film, other insulating films may be used, such as silicon nitride film, deposited by the CVD technique.
The other example of the first structure is disclosed in a U.S. Pat. No. 4,635,090; published on Jan. 6, 1987, which likewise provides a Y-groove structure for solving the degradation of the characteristics due to stress at the upper edge of the U-groove. This U.S. patent states that a silicon oxide film covering the surface of the polysilicon in the Y-groove is formed by a thermal oxidation of the polysilicon. The surface of this silicon oxide film is covered with a silicon nitride film formed by the CVD technique (referred to as "CVD silicon nitride film" hereinafter). Moreover, of the two insulating films, the first is a thermal-oxidation silicon oxide film, and the second is a CVD silicon nitride film both of which are formed over the inner surface of the Y-groove.
In the aforementioned first example, the surface of the U-groove polysilicon is covered with a CVD silicon oxide film. This structure can cause no such stress in the processing steps of forming the dielectric isolation region. In the subsequent steps of forming semiconductor elements, however, the steps of introducing impurities and in addition a processing step for producing a silicon oxide film of a few tens to hundreds nm on the surface of a silicon substrate or a silicon epitaxial layer formed by thermal oxidation are needed for protecting the surface of the silicon substrate of epitaxial layer. This thermal oxidation processing step results in forming a new silicon oxide film over the surface of the U-groove polysilicon, irrespective of the previous presence of the CVD silicon oxide film because O.sub.2 gas can pass substantially freely through the CVD silicon oxide film. In the processing steps of the first example for forming semiconductor elements, this thermal oxidation step reflects a volume-expansion (about 1.5 times) in the vicinity of the surface of the U-groove dielectric isolation region, and thus stress will be applied to the upper portion of the U-groove to enlarge it. This stress may induces crystal lattice defects which in turn can cause a leakage current resulting from breakdown of the p-n junction of semi-conductor element.
In the second example above-mentioned, the surface of a polysilicon inside the Y-groove is covered with a first thermal-oxidation silicon oxide film, and with a silicon nitride film formed over the first film. Thus in the proceeding steps of forming semiconductor elements, no stress occurs resulting from the volume expansion of the surface of the dielectric isolation region of Y-groove structure. On the other hand, the upper edge portion of the Y-groove structure is formed by isotropic etching, and thus it has an average slope of more than 45.degree. C. In this structure, as compared with the U-groove structure in the first example, the stress near the upper edge portion is produced when a thermal-oxidation silicon oxide film is formed on the surface of the polysilicon in the Y-groove. This stress is somewhat lowered, but it still amounts to more than 70%.
As described above, with the prior art U-(and Y-groove) structure commonly used in bipolar semiconductor devices, it is considered impossible to greatly reduce the stress produced in the processing steps of forming the dielectric isolation region of semiconductor elements. For example, bipolar semiconductor devices such as ECL RAM are required because the C-E leakage current may be up to 1/10 of the hold current. The presence of a dislocation relating to the emitter region can cause an increase of C-E leakage current. A similar phenomenon may occur in other bipolar semiconductor devices having different circuitries. A general method in the prior art for suppressing the production of C-E leakage current is to take a sufficiently great distance from the dielectric isolation region to emitter region. This is a major impediment against large-scale integration of bipolar semiconductor devices.